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Freescale Semiconductor /MK10F12 /LMEM /PSCRMR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as PSCRMR

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https://regviz.com/r/Freescale Semiconductor/MK10F12/LMEM/PSCRMR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (00)R150 (00)R140 (00)R130 (00)R120 (00)R110 (00)R100 (00)R90 (00)R80 (00)R70 (00)R60 (00)R50 (00)R40 (00)R30 (00)R20 (00)R10 (00)R0

R13=00, R4=00, R8=00, R11=00, R0=00, R2=00, R3=00, R7=00, R5=00, R6=00, R15=00, R12=00, R9=00, R14=00, R1=00, R10=00

Description

Cache regions mode register

Fields

R15

Region 15 mode

0 (00): Non-cacheable

1 (01): Non-cacheable

2 (10): Write-through

3 (11): Write-back
R14

Region 14 mode

0 (00): Non-cacheable

1 (01): Non-cacheable

2 (10): Write-through

3 (11): Write-back
R13

Region 13 mode

0 (00): Non-cacheable

1 (01): Non-cacheable

2 (10): Write-through

3 (11): Write-back
R12

Region 12 mode

0 (00): Non-cacheable

1 (01): Non-cacheable

2 (10): Write-through

3 (11): Write-back
R11

Region 11 mode

0 (00): Non-cacheable

1 (01): Non-cacheable

2 (10): Write-through

3 (11): Write-back
R10

Region 10 mode

0 (00): Non-cacheable

1 (01): Non-cacheable

2 (10): Write-through

3 (11): Write-back
R9

Region 9 mode

0 (00): Non-cacheable

1 (01): Non-cacheable

2 (10): Write-through

3 (11): Write-back
R8

Region 8 mode

0 (00): Non-cacheable

1 (01): Non-cacheable

2 (10): Write-through

3 (11): Write-back
R7

Region 7 mode

0 (00): Non-cacheable

1 (01): Non-cacheable

2 (10): Write-through

3 (11): Write-back
R6

Region 6 mode

0 (00): Non-cacheable

1 (01): Non-cacheable

2 (10): Write-through

3 (11): Write-back
R5

Region 5 mode

0 (00): Non-cacheable

1 (01): Non-cacheable

2 (10): Write-through

3 (11): Write-back
R4

Region 4 mode

0 (00): Non-cacheable

1 (01): Non-cacheable

2 (10): Write-through

3 (11): Write-back
R3

Region 3 mode

0 (00): Non-cacheable

1 (01): Non-cacheable

2 (10): Write-through

3 (11): Write-back
R2

Region 2 mode

0 (00): Non-cacheable

1 (01): Non-cacheable

2 (10): Write-through

3 (11): Write-back
R1

Region 1 mode

0 (00): Non-cacheable

1 (01): Non-cacheable

2 (10): Write-through

3 (11): Write-back
R0

Region 0 mode

0 (00): Non-cacheable

1 (01): Non-cacheable

2 (10): Write-through

3 (11): Write-back

Links

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data